Treatment of low-k dielectric films to enable patterning of deep submicron features

ABSTRACT

Treating a low-k dielectric layer ( 104 ) using a highly oxidizing wet solution (e.g., H 2 O 2 ) to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( 104 ), such as OSG, and DUV resist ( 130,132 ). The wet treatment is performed to either pre-treat a low-k dielectric ( 104 ) before forming the pattern ( 130,132 ) or during a rework of the pattern ( 130,132 ) to reduce resist poisoning.

FIELD OF THE INVENTION

[0001] The invention is generally related to the field of forminginterconnect layers in a semiconductor device and more specifically topatterning low-k dielectric films.

BACKGROUND OF THE INVENTION

[0002] As the density of semiconductor devices increases, the demands oninterconnect layers for connecting the semiconductor devices to eachother also increases. Therefore, there is a desire to switch from thetraditional aluminum metal interconnects to copper interconnects andfrom traditional silicon-dioxide-based dielectrics to low-k dielectrics,such as organo-silicate glass (OSG). Semiconductor fabrication processesfor working with the copper interconnects and newer low-k dielectricsare still needed.

[0003] Suitable copper etches for a semiconductor fabricationenvironment are not readily available. To overcome the copper etchproblem, damascene processes have been developed. In a damasceneprocess, the IMD is formed first. The IMD is then patterned and etchedto form a trench for the interconnect line. If connection vias have notalready been formed, a dual damascene process may be used. In a dualdamascene process, after the trench is formed in the IMD, a via isetched in the ILD for connection to lower interconnect levels. A barrierlayer and a copper seed layer are then deposited over the structure. Thebarrier layer is typically tantalum nitride or some other binarytransition metal nitride. The copper layer is electrochemicallydeposited (ECD) using the seed layer over the entire structure. Thecopper is then chemically-mechanically polished (CMP'd) to remove thecopper from over the IMD, leaving copper interconnect lines and vias. Ametal etch is thereby avoided.

[0004] When low-k dielectrics such as OSG are used for the IMD and ILD,a problem known as resist poisoning occurs. Resist poisoning occursduring a patterning step such as via pattern or trench pattern. It is aresult of the interaction between a DUV (deep ultra-violet) resist andlow-k films. Resist poisoning causes poor resist sidewall profiles,resist scumming, large CD variations, and requires a large resistexposure dose. Furthermore, the required pattern energy to achieve thetarget CD becomes too high and varies with film aging. A process toreduce or eliminate resist poisoning in low-k dielectrics is thereforedesired.

SUMMARY OF THE INVENTION

[0005] The invention is a treatment for low-k films that improvespatterning. The surface of the low-k film is oxidized using a highlyoxidizing wet solution. Example wet solutions include H₂SO₄:H₂O₂,HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O. The wet solution affects the surface ofthe film rendering patterning possible without disturbing the bulkproperties of the low-k film. Wet treatment can be performed at variousplaces in the semiconductor fabrication process with or without thepresence of resist.

[0006] An advantage of the invention is providing a treatment to reduceresist poisoning of low-k dielectric films.

[0007] This and other advantages will be apparent to those of ordinaryskill in the art having reference to the specification in conjunctionwith the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings:

[0009] FIGS. 1A-1F are cross-sectional diagrams of a process for formingmetal interconnects according to the embodiments of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] The invention will now be described in conjunction with dualdamascene copper interconnect process. It will be apparent to those ofordinary skill in the art that the benefits of the invention may beapplied generally to patterning of low-k (K<3.5???) and ultra-low-k(K<2.5) films.

[0011] In order to form the copper interconnects using a dual damasceneprocess, the interlevel dielectrics (IMD 104 and ILD 102 of FIG. 1A) arepatterned and etched to form trenches in IMD 104 and vias in ILD 102.When low-k or ultra low-k materials are used for the interleveldielectrics, an interaction between the resist pattern and the low-kmaterial causes resist poisoning. The cause of resist poisoning isbelieved to be the interaction of between the DUV resist and nitrogenfrom the low-k films. Possible sources of nitrogen include: the low-kfilm, the silicon nitride cap (if used), N₂ in the clean (ash) process,N₂ in the etch chemistry, use of a silicon-nitride etchstop layer, andthe resist itself.

[0012] In order to reduce or eliminate the resist poisoning, a highlyoxidizing wet treatment is performed on the surface of the low-k films.Only the top monolayers of the low-k film are affects. HOW DOESOXIDIZING THE TOP MONOLAYERS PREVENT RESIST POISONING?

[0013] The bulk properties of the film are unchanged. There is nosignificant change in the thickness, the refractive index, or the FTIRspectra of the low-k films subjected to a highly oxidizing wet solutionaccording to the invention. Example chemistries for the highly oxidizingwet solution include H₂SO₄: H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O. Inthe preferred embodiment, H₂SO₄:H₂O₂ is used at a ratio on the order of4:1 at a temperature on the order of 120° C. and a duration of around 30minutes. WOULD THE WAFERS TYPICALLY BE SET IN A BATH OF THE WETSOLUTION?

[0014] The above treatment using a highly oxidizing wet solution isbeneficial at a variety of places in a metal interconnect process. Theembodiments described below provide examples of where the wet treatmentmay be performed to reduce or eliminate resist poisoning. Theseembodiments may be combined to further reduce or eliminate resistpoisoning.

[0015] Embodiments of the invention will now be discussed with referenceto FIGS. 1A-1F. A semiconductor body 100 is processed through formationof the ILD 102/IMD 104. Semiconductor body 100 typically comprises asilicon substrate having transistors and other elements formed therein.IMD 104 is the dielectric for a copper interconnect level 114. Copperinterconnect level 114 may be the first or any subsequent metalinterconnect level of the semiconductor device 120.

[0016] An ILD 102 is formed over semiconductor body 100. IMD 104 isformed over ILD 102. An etchstop layer (not shown) may optionally beplaced between ILD 102 and IMD 104. ILD 102 and IMD 104 comprise low-kor ultra low-k dielectrics, such as organo-silicate glass (OSG). WHATOTHER CLASSES OF DIELECTRIC MAY BE USED?

[0017] In the preferred embodiment, ILD 102 and IMD 104 comprise thesame material. However, ILD 102 and IMD 104 may alternatively comprisedifferent materials. A capping layer (not shown) may be formed over IMD104 if desired. Typically, the capping layer comprises silicon nitride.Alternatively, a TEOS (tetraethyoxtsilane) capping layer or no cappinglayer may be used.

[0018] In a first embodiment of the invention the wet treatment (using ahighly oxidizing wet solution 136 as described above) is performed priorto forming the via pattern 130. This oxidizes the top monolayers of theIMD 104. SHOULD I SHOWA SEPARATE SURFACE LAYER AT THE SURFACE OF IMD 104AFTER THE WET TREATMENT? Then, the via pattern 130 is formed as shown inFIG. 1B. The wet pre-treatment reduces resist poisoning at the viapattern level.

[0019] It is sometimes necessary to rework a resist pattern. Rework is aprocess of removing the photoresist and/or BARC material forre-patterning. Pattern rework significantly worsens the resist poisoningproblem. Accordingly, in a second embodiment of the invention, the wettreatment (using a highly oxidizing wet solution) may be used to reworkvia pattern 130. The wet treatment both strips the resist pattern andoxidizes the top monolayers of IMD 104.

[0020] After any desired pattern re-work, the via 106 is then etchedthrough IMD 104 and ILD 102, as shown in FIG. 1C. A post etch clean isthen used to remove via pattern 106. WOULD A N2/H2 ASH BE USED HERE? THEPATENT COMMITTEE COMMENTED THAT THE H2O2 SHOULD NOT BE USED WITH THEVIAS OPENED.

[0021] In order to protect the bottom of vias 106 during the subsequenttrench etch, vias 106 may be partially or completely filled. Forexample, a BARC material may be deposited over the structure and etchedback such that BARC material remains only in the vias 106.

[0022] In a third embodiment of the invention, the exposed surfaces ofIMD 104 (and ILD 102 if appropriate) may be pre-treated with the highlyoxidizing wet solution prior to forming the trench pattern. CAN THE WETTREATMENT BE USED AT THIS POINT? Pre-treatment prior to forming thetrench pattern eliminates or reduces resist poisoning at the trenchpattern level.

[0023] After a post etch clean and wet pre-treatment if desired, atrench pattern 132 may be formed over IMD 104, as shown in FIG. 1D. Ifrework of the trench pattern 132 is desired, the wet treatment may beused to rework the trench pattern 132, according to a fifth embodimentof the invention. The wet treatment functions to strip the trenchpattern and reduce resist poisoning at the trench pattern level.

[0024] After any desired pattern rework, a trench 108 is etched in IMD104, as shown in FIG. 1 E. Copper interconnect structures willsubsequently be formed in trench 108. Trench pattern 132 is thenremoved. WOULD A N2/H2 ASH BE USED FOR THIS?

[0025] Barrier layer 110 is deposited over IMD 104 including in trench108 and via 106. Barrier layer 110 functions to prevent copper diffusioninto the ILD and IMD layers. Suitable barrier materials such as Ta/TaNare known in the art. A seed layer is deposited over barrier layer 110.

[0026] Electrochemical deposition (ECD) may then be used to depositcopper layer 124. Various copper ECD processes are known in the art. Inone example, a 3-step process is used. After placing the wafer in theplating solution, a current of approximately 0.75 Amps is passed throughthe seed layer for a time on the order of 15 secs. The current is thenincreased to around 3 Amps for approximately 60 seconds. Final platingoccurs at a current of about 7.5 Amps with the duration determined bythe final desired thickness. A quick spin-rinse dry (SRD) is performedin the plating cell above the plating solution. The wafer is thentransferred to the SRD cell and a post-ECD SRD is used to clean theplating residue.

[0027] After copper ECD, the copper 124 and barrier 110 are chemicallymechanically polished (CMP) to remove the material from above IMD 104.The resulting structure is shown in FIG. 1 F. Processing may thencontinue to form additional metal interconnect levels and package thedevice.

[0028] While this invention has been described with reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. It is therefore intended that the appended claimsencompass any such modifications or embodiments.

1. A method for fabricating an integrated circuit, comprising the steps of: forming a low-k dielectric layer over a semiconductor body; treating a surface of said low-k dielectric layer with a highly oxidizing wet solution; forming a resist pattern over said low-k dielectric layer; and etching said low-k dielectric layer using said resist pattern.
 2. The method of claim 1, wherein said highly oxidizing wet solution comprises H₂O₂.
 3. The method of claim 1, wherein said highly oxidizing wet solution is selected from the group consisting of H₂SO₄:H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O.
 4. The method of claim 1, wherein said low-k dielectric layer comprises organo-silicate glass.
 5. The method of claim 1, wherein said low-k dielectric layer comprises an ultralow-k dielectric layer having a dielectric constant less than 2.5.
 6. The method of claim 1, wherein said treating step occurs prior to forming said resist pattern.
 7. The method of claim 1, wherein said treating step removes said resist pattern as part of a pattern re-work step.
 8. A method of fabricating an integrated circuit having copper metal interconnects, comprising the steps of: forming an interlevel dielectric (ILD) over a semiconductor body; forming an intrametal dielectric (IMD) over the ILD; oxidizing said IMD with a highly oxidizing wet solution; forming a via resist pattern over said IMD; etching a via in said IMD and ILD using said via resist pattern; at least partially filling said via with a material; forming a trench resist pattern over said IMD; etching a trench in said IMD using said trench resist pattern; removing said trench resist pattern and said material in said via; and forming a copper interconnect in said via and said trench.
 9. The method of claim 8, wherein said highly oxidizing wet solution comprises H₂O₂.
 10. The method of claim 8, wherein said highly oxidizing wet solution is selected from the group consisting of H₂SO₄:H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O.
 11. The method of claim 8, wherein said oxidizing step occurs prior to the step of forming the via resist pattern.
 12. The method of claim 11, further comprising the step of additionally treating the IMD using a highly oxidizing wet solution after said step of at least partially filling the via and prior to the step of etching the trench.
 13. The method of claim 8, wherein said oxidizing step occurs after the step of forming the via resist pattern as part of a pattern re-work step.
 14. The method of claim 8, wherein said oxidizing step occurs after said step of at least partially filling the via and prior to the step of etching the trench. 